• State Suggested Answer
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 349 subscribers
  • Views 5174 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

SMP to suspend an individual core with security OS

astonelin@gmail.com

Hi All,

a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.

how to implement a suspend/resume flow on a individual core?

TRM only mentions about how to clean cache and off-line from smp

But how to do a cache flush through/across a secure world environment is properly ? 

Anyone have any comment about this topic ?

Parents
  • 0

    This would depend on the software stack.  Generically you would send a message into the secure world, via an SMC call and the secure software would perform the cache flush and interface with the power controller.

    Arm has a spec called PSCI that provides a template for those messages.  You can see this in action in the linux kernel.

Reply
  • 0

    This would depend on the software stack.  Generically you would send a message into the secure world, via an SMC call and the secure software would perform the cache flush and interface with the power controller.

    Arm has a spec called PSCI that provides a template for those messages.  You can see this in action in the linux kernel.

Children
No data