Hi All,
a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.
how to implement a suspend/resume flow on a individual core?
TRM only mentions about how to clean cache and off-line from smp
But how to do a cache flush through/across a secure world environment is properly ?
Anyone have any comment about this topic ?
This would depend on the software stack. Generically you would send a message into the secure world, via an SMC call and the secure software would perform the cache flush and interface with the power controller.
Arm has a spec called PSCI that provides a template for those messages. You can see this in action in the linux kernel.