Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    Cortexa53 AARCH64 context switch +1

    • Cortex-A53
    • AArch64
    • Cortex-A
    12142 views
    2 replies
    Latest over 6 years ago
    by LdB
  • Answered

    Cortex M7 DSP moving average UMAAL +1

    • Cortex-M7
    • Digital Signal Processor (DSP)
    • Cortex-M
    • CMSIS
    7863 views
    4 replies
    Latest over 6 years ago
    by Mr_M_from_G
  • Not Answered

    Access ETM without using a debug kit 0

    • ETM
    • Cortex-M3
    • Cortex-M
    • Debugger
    10912 views
    13 replies
    Latest over 6 years ago
    by Tony Armitstead Arm Employee Badge
  • Answered

    Reason for Cortex A53 delays +1

    • Raspberry Pi
    • Cortex-A53
    • Cortex-A
    9367 views
    1 reply
    Latest over 6 years ago
    by Zhifei Yang
  • Answered

    The number of big cores in Dynamiq cluster? +1

    • Cortex-A
    • DynamIQ Shared Unit (DSU)
    8399 views
    1 reply
    Latest over 6 years ago
    by Zhifei Yang
  • Answered

    Can I detect from which mode (EL1, EL0,...) SError interrupt was caused? +1

    • RAS Extensions
    • ARMv8 Exception Model
    10292 views
    1 reply
    Latest over 6 years ago
    by a.surati
  • Not Answered

    PMU Register description is not clear in Arm Cortex -R52 Processor Revision: r1p1 0

    • Cortex-R52
    • Cortex-R
    • api
    1626 views
    0 replies
    Started over 6 years ago
    by Reco
  • Answered

    What exactly is a full implementation of ARMv8.2-A? +1

    • Armv8-A
    • Cortex-A75
    • Cortex-A
    • SIMD and Vector Execution
    12597 views
    1 reply
    Latest over 6 years ago
    by a.surati
  • Answered

    XN bit in translation descriptor 0

    • Armv8
    12792 views
    3 replies
    Latest over 6 years ago
    by a.surati
  • Answered

    ARMv8.1-A:How to disable the hardware management of the Access flag +1

    • Armv8.1-A
    8047 views
    1 reply
    Latest over 6 years ago
    by zhangxinxin
  • Answered

    AArch64 TLB maintenance requirements 0

    • AArch64
    • Memory Management Unit (MMU)
    18745 views
    10 replies
    Latest over 6 years ago
    by Michal Meloun
  • Answered

    A question about the access flag fault 0

    • Armv7-A
    • AArch64
    • System Control Register (SCTLR)
    • AArch32
    14833 views
    4 replies
    Latest over 6 years ago
    by stay foolish
  • Not Answered

    ARMv8 AArch64: trapping hardware breakpoint to EL2 0

    • AArch64
    • Armv8-A
    8060 views
    0 replies
    Started over 6 years ago
    by meitarb
  • Answered

    GIC500 + CPU Interface - CA53 +1

    • Cortex-A53
    • Generic Interrupt Controller
    • Cortex-A
    8924 views
    2 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Can't find many microprocessor manufacturers with Cortex-A7 architecture? +1

    • Raspberry Pi
    • Cortex-A9
    • Cortex-A
    • Cortex-A7
    20935 views
    9 replies
    Latest over 6 years ago
    by linda zhang
  • Answered

    L2 TLB internal memory access through RAMINDEX +1

    • Cortex-A57
    • Cortex-A76
    • Cortex-A
    10861 views
    4 replies
    Latest over 6 years ago
    by Amitra29877
  • Answered

    Can we reset L2 subsystem for cortex-A57? +1

    • Cortex-A57
    • Cortex-A
    7845 views
    1 reply
    Latest over 6 years ago
    by MarekBykowski
  • Answered

    what is non-secure callable and when can use it ? 0

    • TrustZone
    • Armv8-M
    11635 views
    3 replies
    Latest over 6 years ago
    by Simon
  • Answered

    Why thumb code can only access r0-r7? 0

    • Armv6-M
    • T32 (Thumb)
    • Arm Thumb Procedure Call Standard (ATPCS)
    • Cortex-M
    5199 views
    4 replies
    Latest over 6 years ago
    by Wenchuan2018
  • Answered

    Behavior for other data on a STR (ARMv7-A) +1

    • Armv7-A
    • Cortex-A
    8080 views
    2 replies
    Latest over 6 years ago
    by superdesk
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone