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Hi,
I’m a little bit confused regarding the atomic operation Cache Sync (REG7_CACHE_SYNC).
How should the maintenance operation used? I have seen an example in XILINX SDK.
void Xil_L2CacheFlush(void)
{
u32 ResultL2Cache;
/* Flush the caches */
/* Disable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x3U);
Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
0x0000FFFFU);
ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
& 0x0000FFFFU;
while(ResultL2Cache != (u32)0U) {
}
Xil_L2CacheSync();
/* Enable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x0U);
/* synchronize the processor */
dsb();
static void Xil_L2CacheSync(void)
Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
Thanks!