Hi
I am a rookie part of a group working on building a Microcontroller, for which we've decided to use AHB Lite protocol with one single master for interconnection. I have thoroughly examined the protocol and am well versed in its behaviour. Our idea is to include a chip separately for bus interconnections that follows AHB-Lite protocol. What I don't understand is how to implement this, i.e. where do all the H-signals originate from? The confusion is what the specification manual means by Master and Slave. Two approaches:
1. Our processor is currently designed with LOAD/STORE architecture that would give out separate sets of signals (instead of AHB signals) to the AHB-Chip. The AHB-Lite chip will then convert these into H-signals in the master interface.
This approach assumes that the "Master", "Slave" and the Decoder-Mux are all present inside a single chip (the AHB-Lite chip) that takes care of interconnection between processor and the memories. In this case I need to take the signals from the processor and make the master interface emit the H-signals accordingly, by writing a FSM for HTRANS logic.
2. Do I need to make the processor give out all HTRANS, HBURST, etc signals by itself? In that case, the effective AHB-Lite chip will only consist of Decoder and Mux.
This approach assumes that the "Master" and "Slave" that the specification manual talks about are actual processor and memory, and directly produce the H-signals. In this case, i need to redesign the processor by including a module within the processor to make it AHBLite compatible.
Thanks in Advance!
Kedhar Guhan
:)