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Hi
I am a rookie part of a group working on building a Microcontroller, for which we've decided to use AHB Lite protocol with one single master for interconnection. I have thoroughly examined the protocol and am well versed in its behaviour.
But by saying master, do we refer to the actual processor or the interface within the AHB-Lite chip for the master?
In an SOC, is there a separate chip for AHB interconnection between processor and memories? What does this chip comprise of?
The architecture block diagram of an AHB-Lite system given in the specification manual refers to the entire SOC or the architecture inside the AHB-Chip? In the former case, master would be the processor, whereas in the latter case master would be just the interface withing the AHB-Lite chip that makes the processor compatible with the protocol.
I'm confused with this fundamental idea of AMBA master-slave architecture. Please shed some clarity.
Thanks in Advance
B Kedhar Guhan
The master is the AHB interface that initiates transfer requests, so the interface that drives HTRANS, HADDR etc.
This will usually be what you refer to as the "processor", but it could be a component downstream from the "processor" which has received a transfer request from the upstream "processor" perhaps on a separate AHB connection to this component, and this component then needs to generate a new request to perform what the upstream "processor" requested. An example of these would be the output of some data width conversion, clock domain crossing or protocol conversion bridge.
So "master" just means any AHB interface that initiates transactions.
As to whether a SOC contains a separate chip to connect the processors and memories, that is something you as the system architect would decide. If the processor and memories are fixed hard macrocells, yes, the AHB interconnecting logic would then be a separate module, but this isn't something the AHB protocol defines. All the protocol tells you is how the master(s) communicate with the slave(s).