Hi,
I have a problem to understand the functionality of double linefill issuing.
In which case the cache controller loads a second cache line from L3 into L2? Where is the difference to prefetch?
According to the documentation:
“When the L2C-310 is waiting for the data from L3, it performs a lookup on the second cache line targeted by the 64-byte linefill.
If it misses, data corresponding to the second cache line are allocated to the L2 cache. If it hits, data corresponding to the second cache line are discarded.”
Maybe somebody can explain when the cache controller performs a 64-byte linefill. I thought if there is a cache miss on L2 the cache controller loads two cache lines from L3 into L2.
Thanks!