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Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped

teamrtos

Hi

I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core.  Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory mapped register space of L2 cache controller (L2C 310) in MMU (Cache is still disabled), exceptions do not come. Not able to figure out what L2 cache controller mapping do without enabling the cache.

Deepak

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