Hi
I am a rookie part of a group working on building a Microcontroller, for which we've decided to use AHB Lite protocol with one single master for interconnection. I have thoroughly examined the protocol and am well versed in its behaviour. Our idea is to include a chip separately for bus interconnections that follows AHB-Lite protocol. What I don't understand is how to implement this, i.e. where do all the H-signals originate from? The confusion is what the specification manual means by Master and Slave. Two approaches:
1. Our processor is currently designed with LOAD/STORE architecture that would give out separate sets of signals (instead of AHB signals) to the AHB-Chip. The AHB-Lite chip will then convert these into H-signals in the master interface.
This approach assumes that the "Master", "Slave" and the Decoder-Mux are all present inside a single chip (the AHB-Lite chip) that takes care of interconnection between processor and the memories. In this case I need to take the signals from the processor and make the master interface emit the H-signals accordingly, by writing a FSM for HTRANS logic.
2. Do I need to make the processor give out all HTRANS, HBURST, etc signals by itself? In that case, the effective AHB-Lite chip will only consist of Decoder and Mux.
This approach assumes that the "Master" and "Slave" that the specification manual talks about are actual processor and memory, and directly produce the H-signals. In this case, i need to redesign the processor by including a module within the processor to make it AHBLite compatible.
Thanks in Advance!
Kedhar Guhan
:)
I'm not too sure how to answer this as you seem to be suggesting 2 different solutions.
1. describes the "AHB-lite chip" performing all of the interfacing between non-AHB components (your processor and memories), so yes, it needs to implement whatever logic is needed to convert the non-AHB processor requests to AHB traffic, and then convert this AHB traffic to the signals needed to interface to the memories.
2. seems to be describing a more AHB integrated solution where the "processor" block already includes an AHB interface, so that the "AHB-lite chip" then only needs to include the AHB interconnecting logic to connect to the downstream slaves, where presumably the memories have also been converted to AHB interfaces.
Both are possible solutions, and whether you have the conversion logic to and from the AHB protocol inside the processor and memory components, or have these conversions as part of the "AHB-lite chip" is something you will decide.
I don't think I have answered your question, but the answer will really depend on the interfaces you have on your processor and memories. The connections to/from these components to the AHB interconnecting logic need to use AHB, but where you implement these conversions isn't really something you can get a generic answer for.