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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3584 Questions
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  • Not Answered

    Is this procedure to get A53 to read/write (test) the L1D cache feasible. 0

    738 views
    0 replies
    Started over 1 year ago
    by User_0182
  • Answered

    cortex-m3 cycle model +1

    • Cycle Models
    • Cortex-M3
    • License Management
    1175 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Does Cortex-R8 support Coresight SoC-600? 0

    1401 views
    1 reply
    Latest over 1 year ago
    by Stuart Hirons Arm Employee Badge
  • Answered

    R5F mbif file +1

    1715 views
    2 replies
    Latest over 1 year ago
    by Junkai Sun
  • Not Answered

    NEON optimisation techniques for cortex-A35 0

    708 views
    0 replies
    Started over 1 year ago
    by Muhammed Fasil K
  • Not Answered

    CurrentEL value on android armv8-a 0

    • Android
    • Armv8-A
    1405 views
    1 reply
    Latest over 1 year ago
    by Annie
  • Not Answered

    TF-M Support 0

    • Trusted Firmware-M
    • Security
    • STM32
    1771 views
    3 replies
    Latest over 1 year ago
    by Tiffany Lin Arm Employee Badge
  • Suggested Answer

    Why there is restrictions on WriteUnique and WriteLineUnique usage in AMBA ACE protocol? 0

    • AMBA 4
    1776 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Cortex-X : Next generation 0

    1786 views
    2 replies
    Latest over 1 year ago
    by Jerome Decamps - 杜尚杰
  • Not Answered

    Cortex-v7M MPU reprogramming 0

    1052 views
    0 replies
    Started over 1 year ago
    by amk
  • Not Answered

    [Cortex-A15/Arm7v]Is the way to disable the speculative memory accesses of L1 0

    • Cortex-A15
    2173 views
    4 replies
    Latest over 1 year ago
    by Y.Im
  • Not Answered

    Using SSE-200 MPU to modify specific region from normal to device memory 0

    771 views
    0 replies
    Started over 1 year ago
    by SarahW
  • Not Answered

    Cotex M4 + FreeRTOS -- CPU register cleared after wfi/sleep mode 0

    • Cortex-M4
    • STM32 F3
    1321 views
    0 replies
    Started over 1 year ago
    by Martin Wagner
  • Answered

    LDR (literal) instruction VR Field meaning 0

    • Memory Access Instructions
    2157 views
    2 replies
    Latest over 1 year ago
    by ADJ
  • Not Answered

    Instruction fetch alignment 0

    • Cortex-A
    • Instruction Fetch
    997 views
    0 replies
    Started over 1 year ago
    by rkd
  • Suggested Answer

    could the Rready signal be asynchronous with aclk? 0

    1035 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Atomic transaction AMBA 5 0

    1678 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    RAS Fault injection on A78AE 0

    • Cortex-A78AE
    823 views
    0 replies
    Started over 1 year ago
    by irodrigu
  • Not Answered

    A53 latencies / jitter (memory access)? 0

    • Cortex-A53
    • Memory
    933 views
    0 replies
    Started over 1 year ago
    by linuxonarm
  • Answered

    Estimate timing cycle of udiv instruction. 0

    • Cortex-M4
    2639 views
    3 replies
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
<>
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