Does Cortex-A53 put stack in L1 data cache when the region is marked as uncacheable? ?

Hi everybody, 

I am writing a program to put debug data in the 32KB L1 Data cache, then read back via method in A53 TRM section 6.7) direct access to internal memory. 

I disable the data cache then put zero in DDR at address 0-32KB, then enable/invalidate data cache and do a sum of that 32KB. In theory A53 would move that 32K from DDR to L1D. 

Then I read back the L1D, small portion of the data are non-zero, through the tag values I can trace the contamination to contents near the stack. 

My program is stored in DDR region 16-24MB which I marked as NORM_NONCACHE. The program is approx. 20KB and works at EL3/baremetal with JTAG debugger attached.

What might have gone wrong with my method? 

Thank you.