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The Inventors Challenge Ceremony 2022

Background Arm and All India Council for Technical Education have academic partnership and signed…

Apurva Varma
The Inventors Challenge: semifinalists details

Serial Number Faculty Name Name of the students in the Team Institute Name Name of the…

Suriya Gunasekaran
Evaluation Criteria for Idea Submission - Inventors…

Please find the evaluation criteria below. You can download the criteria at the end of this post. If…

Apurva Varma
Evaluation team profiles

Alok Mittal Senior Group Manager SRA, Innovation and Collaborations – APAC STMicroelectronics…

Oliver Beirne

Not Answered
What is the unit of PMHF for R52 IP FMEDA 0
- Cortex-R52
141 views

0 replies

Started 26 days ago
by pengfu xie
Answered

Equivalent of SSE4.2 needed for ARM support to CNDP Project 0

853 views

6 replies

Latest 29 days ago
by Annie
Not Answered

ARMV8 arch64 how to handle bus error and interrupt occur together 0

645 views

2 replies

Latest 29 days ago
by Thomas Coding
Not Answered

Cortex-M7 Failing to read PPB ROM table 0

173 views

0 replies

Started 29 days ago
by Bert Hindle
Not Answered

Debug Print Logs Display and Hardware Power Issue in KEIL uVision 5 (Cortex-M0) 0

249 views

1 reply

Latest 30 days ago
by Annie
Not Answered
SMMUv2 IRQS per Context Bank 0
- SMMUv2
160 views

0 replies

Started 1 month ago
by Jorge
Not Answered
The pipeline of add with lsl >4 in Neoverse N1 0
- Documentation
- Neoverse N1
298 views

0 replies

Started 1 month ago
by Juneyoung Lee
Not Answered
Can I use a Single Linux OS to schedule two DSU cluster? 0
- Embedded Linux
- DynamIQ
523 views

3 replies

Latest 1 month ago
by Martin Weidmann
Suggested Answer
Enabling MPU causes clearing of Stack in Cortex R5F 0
- Cortex-R5
256 views

1 reply

Latest 1 month ago
by Martin Weidmann
Not Answered
Tail Chaining 0
- Interrupt Handling
357 views

1 reply

Latest 1 month ago
by Sue Wu
Suggested Answer
Is PendSV or counterpart available on Cortex-A? 0
- Cortex-A
- 14 (PendSV)
391 views

2 replies

Latest 1 month ago
by AndyBlue
Suggested Answer

Cortex-A78 NEON instructions timing 0

317 views

1 reply

Latest 1 month ago
by Zhifei Yang
Answered
How to obtain the AArch64 memory management examples mentioned in the document "Learn the architecture - AArch64 memory management examples" 0
501 views

4 replies

Latest 1 month ago
by zhanlang
Not Answered

Arm 0

206 views

0 replies

Started 1 month ago
by Sebastienjessu8098
Answered
Cortex-M4F: Assembly instruction SMLAxy (and some others) gives wrong result 0
- Cortex-M4
466 views

2 replies

Latest 1 month ago
by Evgen Volkov
Suggested Answer
What's the relationship between trace and SPE? 0
- performance
- arm streamline
298 views

1 reply

Latest 1 month ago
by Ronan Synnott
Not Answered

ARMv8 trigger core dump 0

336 views

2 replies

Latest 1 month ago
by Pete_Gil
Not Answered

A53: PMU - BUS_ACCESS_LD - Write-Streaming 0

325 views

0 replies

Started 1 month ago
by Chris_Ger
Not Answered
CYCLONE V - HPS - DDR RAM CONTROL OVER JTAG WITH OPENOCD 0
- Cortex-A9
- JTAG
- SoC FPGA
- Baremetal
206 views

0 replies

Started 2 months ago
by ieeeHuseyin
Suggested Answer

NIC400: What is the difference between ahblitetarget and ahbliteinitiator 0

338 views

1 reply

Latest 2 months ago
by Colin Campbell