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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
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  • Not Answered

    Support of immediate Rorate & Shift in STM32 CortexM4 0

    • Cortex-M4
    907 views
    0 replies
    Started over 3 years ago
    by N Abid Ali Khan
  • Not Answered

    Include macro in .s file 0

    3367 views
    2 replies
    Latest over 3 years ago
    by WestfW
  • Not Answered

    Cannot flash or erase the STM32 uC anymore. 0

    2181 views
    1 reply
    Latest over 3 years ago
    by HenkvW
  • Answered

    Cortex-A32 aarch32, change from HYP mode to SVC mode fail 0

    1482 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    [Cortex-A] Permission fault due to code region mapped as read/write 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    • Cortex-A
    3425 views
    5 replies
    Latest over 3 years ago
    by jatron
  • Not Answered

    Cortex A9 L1d cache profiling 0

    • Cortex-A9
    • performance analysis
    • Cache Controllers
    1504 views
    1 reply
    Latest over 3 years ago
    by Noemietown
  • Not Answered

    Activate ETM in Android Mobile device 0

    • mobile
    • Android
    • CoreSight ETM-A5
    • Debug and Trace
    1383 views
    0 replies
    Started over 3 years ago
    by Seongyun
  • Not Answered

    arm cortex a9 used in control edge plc 0

    810 views
    0 replies
    Started over 3 years ago
    by saneesh
  • Not Answered

    .rodata alignment 0

    • AArch64
    • GNU Assembler
    1286 views
    0 replies
    Started over 3 years ago
    by BobP
  • Suggested Answer

    In order execution 0

    1235 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Suggested Answer

    How to control the Non-Secure MPU exclusively inside the Secure world in the Cortex M33? 0

    • Memory Protection Unit (MPU)
    • TrustZone
    • Cortex-M33
    1857 views
    1 reply
    Latest over 3 years ago
    by Aurelien_Grange
  • Not Answered

    start second core from psci 0

    • AArch64
    • SMCCC
    • Cortex-A55
    • Armv8-A
    • psci
    • AArch32
    1375 views
    0 replies
    Started over 3 years ago
    by Nikita bogatov
  • Suggested Answer

    Arm MMU configuration works on (qemu) raspberry(a53) but not on virt(armv7, a53) board 0

    • Cortex-A53
    3687 views
    5 replies
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [armv8][cortex-a72] why must flush data cache when I tried to map a SRAM area? 0

    • Armv8-A
    2400 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    CCA in Armv9 - Making Peripherals Only Accessible from a Realm VM 0

    • virtualization
    • Peripheral Controllers
    • TrustZone
    2071 views
    2 replies
    Latest over 3 years ago
    by Jay M.
  • Suggested Answer

    SError interrupt due to LDAXRB instruction when disable cache on NXP ls1046a 0

    • Armv8-A
    2285 views
    2 replies
    Latest over 3 years ago
    by Tony Tu
  • Suggested Answer

    Does the Arm Cortex-52+ support multi-core / cache coherent / SMP configurations? 0

    • Cortex-R52
    • Cache coherency
    • Cortex-R52+
    3257 views
    3 replies
    Latest over 3 years ago
    by EllieC Arm Employee Badge
  • Not Answered

    Clear recvBuff 0

    936 views
    0 replies
    Started over 3 years ago
    by Rishikeshb1998
  • Not Answered

    Power consumption of CM7 - is there a comparison between manufacturing nodes? 0

    878 views
    0 replies
    Started over 3 years ago
    by Tani
  • Answered

    CCA in Armv9 - Could Realm Management Monitor Check Realm VM's Data? 0

    • virtualization
    • Trusted Execution Environment (TEE)
    2170 views
    3 replies
    Latest over 3 years ago
    by djordje kovacevic Arm Employee Badge
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