Hello all,
I am trying to find resources to turn off prefetchers (l1 and l2) for cortex a72.
So far I have been trying to understand https://developer.arm.com/documentation/100095/0001/level-2-memory-system/l2-cache-prefetcher But I am not sure how to write into these registers
I am familiar with intel and the instructions (read: wrmsr and rdmsr ) to read into model-specific registers but I couldn't find any for arm.
Is there any resource that can help me write into these registers and also mention the caveats [privileges required etc ] for writing ?
Thanks & Regards
Anilava
The system register access instructions in A64 are MRS (https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/MRS--Move-System-Register-?lang=en) and MSR (https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/MSR--register---Move-general-purpose-register-to-System-Register-?lang=en). And there's a general into to the A64 Isa here https://developer.arm.com/documentation/102374/latest/
You can find the register's access permissions here: https://developer.arm.com/documentation/100095/0003/System-Control/AArch64-register-descriptions/CPU-Extended-Control-Register--EL1?lang=en#way1382037668638__CIHEGIIF
But note footnotes (a) and (b). Access to the register at EL1 and EL2 is controlled by ACTLR_EL3 (https://developer.arm.com/documentation/100095/0003/System-Control/AArch64-register-descriptions/Auxiliary-Control-Register--EL3?lang=en)
But more practically - how you go about this will depend on the kind of environment you're working in. As in, is this a bare metal environment or something like a Linux stack.
Can you suggest some resources to do this from Linux stack?
Bare metal I am not so familiar with nonetheless if that has more resources even that works
Disable L1 data cache and unified L2 cache . Disable the load-store hardware prefetcher. This applies only to revision <= r0p3 of Cortex A72.
klondike solitaire
The Load/store unit includes a hardware prefetcher that is responsible for generating prefetches targeting both the L1D cache and L2 cache.
Prefetching on loadsThe load side prefetcher uses a hybrid mechanism which is based on both physical-address (PA) and virtual-address (VA) prefetching to either or both of the L1D cache and L2 cache, depending on the memory access patterns.
Prefetching on storesPrefetching on store accesses is managed by a PA based prefetcher and only prefetches to the L2 cache.
The Load/Store HW prefetcher can be controlled in the following manner using software programmable bits:
Disable the Load/Store HW prefetcher:The load/store HW prefetcher can be disabled by setting the CPUACTLR_EL1 bit .
Disable VA based prefetch: When set, prefetch is restricted to within the page boundary of the demand request triggering that triggers the prefetch.
Disable prefetch on store:
Maximum load prefetch distance to L2:You can control the maximum prefetch distance to the L2, for load side prefetching, by programming bits [33:32] of the CPUECTLR_EL1 register.
Regards,
Rachel Gomez