I recently have been testing the direct internal memory access of the Cortex A53 on the Xilinx ultrascale+ SoC, most notably to access the L1 data cache (data portion) and L1 instruction cache (data portion). I can successfully access the contents of both caches through the CP15 operations as described in the TRM but the issue I'm facing is that after disabling the instruction cache, the content in instruction cache is different when comparing previous reads on the instruction cache. The TRM has a section on the behavior of disabling the instruction cache but nothing that would explain the instruction cache contents changing other than perhaps cache maintenance operations (which I am not directly running). The procedure I have been using to test this behavior is:
The result of this procedure is that multiple (probably more than 50 or so) print messages appear notifying a difference between the array with the instruction cache contents and the current instruction contents. I can perform the same procedure on the L1 data cache that results in not receiving any print messages which is expected but not the instruction cache. It's completely possible that I am not accessing or storing the instruction cache correctly but the data cache I implemented is working as expected and I have made the necessary changes so that the instruction cache should perform in a similar way by using the TRM section on accessing the instruction cache. This brings me to a couple of questions:
Any help would be greatly appreciated. Thank you.
The disabled behavior means that fetches won't trigger lookups or allocations, but the cache will continue to be used for internal buffering (this usage is associated with the pre-decoder).
That would make sense. Thank you for the response, Eugene. I imagine this means that there is no way to prevent the cache being used for internal buffering?
Yes. Disabling instruction cache does not seem to meet your purpose.