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Turn off prefetchers for cortex a72

Anilava

Hello all,

I am trying to find resources to turn off prefetchers (l1 and l2) for cortex a72.

So far I have been trying to understand https://developer.arm.com/documentation/100095/0001/level-2-memory-system/l2-cache-prefetcher 

But I am not sure how to write into these registers

I am familiar with intel and the instructions (read: wrmsr and rdmsr ) to read into model-specific registers but I couldn't find any for arm.

Is there any resource that can help me write into these registers and also mention the caveats [privileges required etc ]  for writing ? 

Thanks & Regards 

Anilava

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    The Load/store unit includes a hardware prefetcher that is responsible for generating prefetches targeting both the L1D cache and L2 cache.

    Prefetching on loads
    The load side prefetcher uses a hybrid mechanism which is based on both physical-address (PA) and virtual-address (VA) prefetching to either or both of the L1D cache and L2 cache, depending on the memory access patterns.

    Prefetching on stores
    Prefetching on store accesses is managed by a PA based prefetcher and only prefetches to the L2 cache.

    The Load/Store HW prefetcher can be controlled in the following manner using software programmable bits:

    Disable the Load/Store HW prefetcher:
    The load/store HW prefetcher can be disabled by setting the CPUACTLR_EL1 bit .

    Disable VA based prefetch:
     When set, prefetch is restricted to within the page boundary of the demand request triggering that triggers the prefetch.

    Disable prefetch on store:

    Maximum load prefetch distance to L2:
    You can control the maximum prefetch distance to the L2, for load side prefetching, by programming bits [33:32] of the CPUECTLR_EL1 register.

    Regards,

    Rachel Gomez

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  • 0

    The Load/store unit includes a hardware prefetcher that is responsible for generating prefetches targeting both the L1D cache and L2 cache.

    Prefetching on loads
    The load side prefetcher uses a hybrid mechanism which is based on both physical-address (PA) and virtual-address (VA) prefetching to either or both of the L1D cache and L2 cache, depending on the memory access patterns.

    Prefetching on stores
    Prefetching on store accesses is managed by a PA based prefetcher and only prefetches to the L2 cache.

    The Load/Store HW prefetcher can be controlled in the following manner using software programmable bits:

    Disable the Load/Store HW prefetcher:
    The load/store HW prefetcher can be disabled by setting the CPUACTLR_EL1 bit .

    Disable VA based prefetch:
     When set, prefetch is restricted to within the page boundary of the demand request triggering that triggers the prefetch.

    Disable prefetch on store:

    Maximum load prefetch distance to L2:
    You can control the maximum prefetch distance to the L2, for load side prefetching, by programming bits [33:32] of the CPUECTLR_EL1 register.

    Regards,

    Rachel Gomez

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