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Cortex-A32 aarch32, change from HYP mode to SVC mode fail

Thomas-coding
Hi,
  
Base info:
core: Cortex-A32
before cpsr: 0x600001da (HYP mode)
  
I want to use below core to change to SVC mode but fail, after below code run, I can jump to 'continueBoot' , But the CPSR still is 0x600001da (HYP mode).
  
What is the method of switching from HYP mode to SVC mode for Cortex-A32? Anything else need to configure?
  
change_to_svc:
		ldr r0, =0x1d3
		msr spsr_hyp, r0
		ldr r0, =continueBoot
		msr elr_hyp, r0
		eret
		nop

continueBoot: /* Continue with bootup */
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  • 0

    I think the problem is "msr spsr_hyp, r0"

    The version of MSR you're using is "Banked Register".  If you take a look at section F5.2.2 of the Arm ARM (Rev I.a), it gives restrictions on when using the Banked Register form.  The summary is, you're only meant to use it for registers not ordinarily accessible.  For Hyp mode (EL2) SPSR_Hyp is the regular SPSR, so you shouldn't be using it this version of the instruction.

    This means that the banked registers that MRS (banked register) and MSR (banked register) instructions cannot access
    are:

    ...

    From Hyp mode
    • The Monitor mode registers SP_mon, LR_mon, and SPSR_mon.
    • The current mode registers R8_usr-R12_usr, SP_hyp, LR_usr, and SPSR_hyp

    The result is that your code is technically UNPRED.  To fix, replace the current MSR with something like"

    MSR     spsr_cxsf, #Mode_SVC
Reply
  • 0

    I think the problem is "msr spsr_hyp, r0"

    The version of MSR you're using is "Banked Register".  If you take a look at section F5.2.2 of the Arm ARM (Rev I.a), it gives restrictions on when using the Banked Register form.  The summary is, you're only meant to use it for registers not ordinarily accessible.  For Hyp mode (EL2) SPSR_Hyp is the regular SPSR, so you shouldn't be using it this version of the instruction.

    This means that the banked registers that MRS (banked register) and MSR (banked register) instructions cannot access
    are:

    ...

    From Hyp mode
    • The Monitor mode registers SP_mon, LR_mon, and SPSR_mon.
    • The current mode registers R8_usr-R12_usr, SP_hyp, LR_usr, and SPSR_hyp

    The result is that your code is technically UNPRED.  To fix, replace the current MSR with something like"

    MSR     spsr_cxsf, #Mode_SVC
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