In AXI protocol, if master issues a transaction to a slave(DRAM) and assume Slave (DRAM) clock is not running. In this case what is response received by the master? will interconnect gives decode error in this scenario?
Ask yourself why was the clock not running if it was needed ?
The system needs to know when the DRAM clock is required, and so you would need some sort of clock controller to know when the clock can safely be disabled, and the system then needs to be configured to handle what will happen to any DRAM request.
If a generic interconnect just receives a request to a target clock domain that isn't being clocked, the transaction will just stall until a response is returned from that domain.
So if there was clock domain control logic implemented as part of the interconnect, the stalled transaction request would need to trigger a clock enable request to the clock controller.
Alternatively when the system clock controller decides to stop the DRAM clock, it could change the interconnect's address map so that the DRAM is no longer seen in the address map, and the access would then be targeting an address that doesn't map on to a target and so receives a DECERR response.
That DECERR could then trigger an abort handler in the request source, with the abort handler then checking to see that the clock is enabled before reconfiguring the interconnect to restore the DRAM to the address map, and then finally repeating the failed DRAM access to the now hopefully clocked DRAM.
So you can't just remove a clock and hope the system will somehow know what to do if the clock is then needed. You need to plan in support for how to implement clock stopping.
Ways to fix-
#1) Update Drivers#2) Update BIOS#3) Disable C1-E In BIOS#4) Reset BIOS#5) Remove Over Clocking Feature#6) Update SSD Firmware#7) Increase RAM#8) Update Windows#9) Run SFC#10) Run Memtest/Windows Memory Diagnostic#11) Run System Restore#12) Troubleshoot in Clean Boot State#13) Run Windows Troubleshooter
Greeting,
Rachel Gomez