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Architectures and Processors forum
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3051 Questions
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  • Answered

    Justification for write-back of UniqueClean line for WriteEvictFull CHI opcode. +1

    • AMBA 5 CHI
    388 views
    2 replies
    Latest 3 months ago
    by nizam.ahmed
  • Not Answered

    ARMv7 TLB dump decoding 0

    • Armv7-A
    • Cortex-A5
    504 views
    2 replies
    Latest 3 months ago
    by Strong
  • Not Answered

    Unrolling a loop 0

    • Cortex-A53
    266 views
    2 replies
    Latest 3 months ago
    by Zvi Vered
  • Suggested Answer

    ARMv8-A Cortex-A72: Generic timer is backoff 0

    • Cortex-A72
    • Armv8-A
    605 views
    1 reply
    Latest 3 months ago
    by Zhifei Yang
  • Answered

    Reverse engineering ARM firmware: selecting an architecture with a superset of features when importing ARMv7/ARMv8 firmware into Ghidra +1

    477 views
    1 reply
    Latest 3 months ago
    by Zhifei Yang
  • Suggested Answer

    [ACE] Why CleanUnique must write back to memory? 0

    313 views
    1 reply
    Latest 3 months ago
    by Zhifei Yang
  • Not Answered

    Unaligned memory access fault with STRH on Cortex-M7 0

    • Cortex-M7
    • 3 (HardFault)
    • 6 (UsageFault)
    550 views
    5 replies
    Latest 3 months ago
    by alexxs88
  • Answered

    M0 SPI outputting 16bit not 8bit 0

    • Cortex-M0
    360 views
    1 reply
    Latest 3 months ago
    by MikeH32096
  • Not Answered

    STM32F103 - Switching from JTAG to SWD 0

    • SWD
    182 views
    0 replies
    Started 3 months ago
    by SamPfarrer
  • Answered

    Linux mmap'ed access with memset() gives an alignment issue on the newer Linux kernels 0

    • Embedded Linux
    • Armv8.1-A
    365 views
    1 reply
    Latest 3 months ago
    by andreas2025
  • Answered

    Delay of "SVC" 0

    • Cortex-R
    • Armv7 Exception Model
    • Cortex-R5
    • Armv7-R
    • 11 (SVCall)
    370 views
    1 reply
    Latest 3 months ago
    by Nowian
  • Answered

    GPT and Caching +1

    523 views
    1 reply
    Latest 3 months ago
    by Martin Weidmann
  • Answered

    Cortex R5 vs R5F +1

    • Cortex-R5
    586 views
    2 replies
    Latest 4 months ago
    by Oliver Beirne
  • Suggested Answer

    IRQ not firing when in SVC call 0

    • Interrupt Handling
    • AArch64
    326 views
    1 reply
    Latest 4 months ago
    by Martin Weidmann
  • Not Answered

    STM32F030K6T6TR Able to program 1st time 0

    • STM32 F0
    330 views
    0 replies
    Started 4 months ago
    by MikeH32096
  • Not Answered

    PMU cyclic counter not updating for cortex r52 0

    313 views
    1 reply
    Latest 4 months ago
    by Annie
  • Answered

    How the PE accesses peripherals registers and memories? 0

    • Peripheral Devices
    • SMMUv3
    403 views
    3 replies
    Latest 4 months ago
    by Martin Weidmann
  • Answered

    How to distinguish B<c>.W and DSB commands in ARMv7M architecture +1

    748 views
    2 replies
    Latest 4 months ago
    by Oliver Beirne
  • Answered

    Question about SMMU 0

    • SMMUv3
    448 views
    1 reply
    Latest 4 months ago
    by Martin Weidmann
  • Suggested Answer

    Relationship between PSEL and PENABLE signals in the APB Protocol. 0

    • APB
    • Protocols
    • Bus Interface
    • AMBA 3 APB Interface
    • SoC Verification
    440 views
    1 reply
    Latest 4 months ago
    by Colin Campbell
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