Synchronous FPU Exception in Cortex R5

Hi expert,

I am working with a Cortex-R5F (specifically the TI AM263P4 SoC) and I am trying to determine the exact instruction address (PC) that causes a floating-point divide-by-zero.

Current Setup:

I have enabled the DZC propagation bit in the Secondary Auxiliary Control Register (c15, Bit 9).
I have configured the VIM (Interrupt Controller) to catch the FPU exception signal.
The interrupt triggers correctly when a division by zero occurs.

The Problem:
Because the FPU pipeline is decoupled and the exception is imprecise/asynchronous, the CPU "slips" and executes many instructions past the faulting one before the ISR is entered. Consequently, the Link Register (LR) in my ISR does not point to the actual instruction that caused the error, making it impossible to debug the root cause in complex codebases.

My Questions:

Is there any architectural configuration for the R5F to force a synchronous trap (Data Abort or Undef) specifically for FPU exceptions?
If the FPU is strictly non-trapping, is there a recommended hardware feature that can capture the faulting instruction address?
Is there any way I can make the CPU wait till FPU is done, so that the once ISR fires, the PC will be at the instruction that caused the issue?

Your feedback would be extremely helpful.

Thanks & Regards,

Aswin