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Architectures and Processors forum
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3060 Questions
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  • Answered

    AXI4 narrower transactions for AWADDR 0

    • AXI4-Lite
    • AXI4
    • Arm64
    546 views
    1 reply
    Latest 10 months ago
    by Colin Campbell
  • Suggested Answer

    Changing the target Security state of an exception 0

    • TrustZone
    • Cortex-M33
    • Armv8-M
    542 views
    1 reply
    Latest 10 months ago
    by Zhifei Yang
  • Suggested Answer

    MPAM REGISTERS ACCESS 0

    • Cortex-A53 FVP
    • Cortex-A
    702 views
    1 reply
    Latest 10 months ago
    by Zhifei Yang
  • Suggested Answer

    What are the different between the MCU cpu and MPU cpu 0

    798 views
    1 reply
    Latest 10 months ago
    by Zhifei Yang
  • Not Answered

    CPU load is higher in M7 than M4 micro 0

    332 views
    0 replies
    Started 10 months ago
    by Bhaskar_ankireddypalli
  • Answered

    Can I create application only with .C file? +1

    583 views
    3 replies
    Latest 10 months ago
    by WestfW
  • Not Answered

    How are created Startup with startup_stm32f4xx.s, Application with Hello.c, CMSIS with system _stm_32f4xx.c,stm32f4xx.h and system_stm32f4xx.h?I would make device with scanf,printf ,what will read, write data to internal flash(if it is possible) 0

    329 views
    0 replies
    Started 10 months ago
    by Pero Kacov
  • Not Answered

    How are created Startup with startup_stm32f4xx.s, Application with Hello.c, CMSIS with system _stm_32f4xx.c,stm32f4xx.h and system_stm32f4xx.h?I would make device only with scanf and printf ,what will read, write data to internal flash(is it is possible 0

    297 views
    0 replies
    Started 10 months ago
    by Pero Kacov
  • Suggested Answer

    What's the purpose of directing hready to the same slave which generated it? Is that necessary? Is it to support a bus kind of hready signal? 0

    483 views
    1 reply
    Latest 10 months ago
    by Colin Campbell
  • Answered

    Armv8-A A55 baremetal boot exception level from EL1 to EL0 0

    • EL0
    • Arm64
    817 views
    4 replies
    Latest 10 months ago
    by zhuxiya
  • Suggested Answer

    AXI5 Atomic transaction 0

    1075 views
    7 replies
    Latest 10 months ago
    by Colin Campbell
  • Not Answered

    How do I detect a USB connection using information in Cortex M7 registers 0

    • Cortex-M7
    407 views
    0 replies
    Started 10 months ago
    by JimD
  • Suggested Answer

    bus problems 0

    785 views
    3 replies
    Latest 10 months ago
    by Colin Campbell
  • Not Answered

    Nonpredicted instruction 0

    306 views
    0 replies
    Started 10 months ago
    by Youq
  • Not Answered

    HSE,HSI,PLL_M,PLL_N,PLL_P,PLL_Q,PLL_R 0

    283 views
    0 replies
    Started 10 months ago
    by Pero Kacov
  • Not Answered

    How to configure Corstone SSE-300 to allow code outside ITCM region? 0

    608 views
    2 replies
    Latest 10 months ago
    by Tobias E
  • Not Answered

    Is there something similar to CMSIS for 8-bit microcontrollers? 0

    • Arduino IDE
    369 views
    1 reply
    Latest 10 months ago
    by jonnysa
  • Suggested Answer

    Instruction Cache Throttle PMU event 0

    435 views
    2 replies
    Latest 10 months ago
    by vstehle
  • Suggested Answer

    How to config AXI4 outstanding by NIC400 0

    1121 views
    3 replies
    Latest 10 months ago
    by Colin Campbell
  • Suggested Answer

    How long does it take to switch working states? 0

    • Armv7 Exception Model
    1074 views
    2 replies
    Latest 10 months ago
    by Annie
<>
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