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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3583 Questions
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  • Not Answered

    Setting MPU_RASR for Memory Protection Unit with correct values of TEX/C/B/S bits 0

    4006 views
    1 reply
    Latest over 5 years ago
    by Uma Ramalingam Arm Employee Badge
  • Not Answered

    Cortex M3 System Design - Simulation Environment 0

    4339 views
    2 replies
    Latest over 5 years ago
    by Brixton
  • Not Answered

    uart problem!! 0

    3853 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Abstraction layer for multiple vendors 0

    4092 views
    4 replies
    Latest over 5 years ago
    by pietro
  • Answered

    Cortex M4 and ARM FIR Q15 Hardfault 0

    • Library
    • CMSIS
    • Cortex-M4
    4870 views
    1 reply
    Latest over 5 years ago
    by KoRba
  • Not Answered

    Debugging using DS5 and Foundation model: Interrupt is not forwarded to the CPU. 0

    • AArch64
    • GICv2
    • DS-5 Ultimate Edition
    • Armv8 Foundation Platform
    • DS-5 Technical Support
    23280 views
    4 replies
    Latest over 5 years ago
    by Jorge
  • Not Answered

    arm CC compiler on ARM cortex a53 0

    23436 views
    3 replies
    Latest over 5 years ago
    by khan777
  • Not Answered

    ACE VIP 0

    18956 views
    0 replies
    Started over 5 years ago
    by Enthusiastic learner
  • Not Answered

    Unusual time in booting secondary cores on ARMV8 platform (Zynq MPSoc) 0

    • Power state coordination Interface
    • Armv8-A
    • TrustZone
    21470 views
    2 replies
    Latest over 5 years ago
    by Saud
  • Not Answered

    Hi ARM, Hi ARM, hardfault_handler() 0

    3581 views
    3 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    How to realise a dual-core "LOCK-STEP" Cortex-M7 at the integration level? 0

    7800 views
    2 replies
    Latest over 5 years ago
    by Uma Ramalingam Arm Employee Badge
  • Not Answered

    Cannot access Memory (@ 0xe000edf0, Read, Acc Size: 4 Byte) 0

    • ulinkpro
    • Cortex-M4
    12337 views
    6 replies
    Latest over 5 years ago
    by c m
  • Not Answered

    cortex M4 boot issue 0

    7907 views
    5 replies
    Latest over 5 years ago
    by d.ry
  • Answered

    LEARNING | Development Boards 0

    • Analog & Asynchronous Design
    • Development Boards
    • Internet of Things (IoT)
    26178 views
    4 replies
    Latest over 5 years ago
    by Andy Neil
  • Answered

    Shared libraries and PLT using GCC toolchain 0

    • GNU Arm
    6194 views
    2 replies
    Latest over 5 years ago
    by rgujju
  • Not Answered

    Forced Hardfault (INVPC) when FreeRTOS on cortext-M33 in non secure mode 0

    4804 views
    2 replies
    Latest over 5 years ago
    by Valentin Nechunaev
  • Not Answered

    How can I configure BTAC and GHB size? 0

    20665 views
    0 replies
    Started over 5 years ago
    by w38245
  • Not Answered

    Cortex M4 and M7 comparison for CMSIS DSP function 0

    3256 views
    1 reply
    Latest over 5 years ago
    by sunil rathod9
  • Not Answered

    what is the clock cycles overhead for context switch in trust zone? 0

    • Cortex-M23
    • TrustZone
    • Cortex-M33
    6590 views
    5 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    SPI on STM32F407 Discovery not working 0

    3720 views
    2 replies
    Latest over 5 years ago
    by Andy Neil
<>
Topics being discussed in this forum
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