How to realise a dual-core "LOCK-STEP" Cortex-M7 at the integration level？

Cortex-M7 has a parameter named LOCKSTEP to configure whether the implementation is a dual-redundant core.

It is related to functional safety requirements in certain types of microcontrollers/SoC for automotives and industrial applications. This allows logic failures to be detected, which enables safety features to kick in and start remedy actions.

The link below is a paper published in Embedded World 2015, which covered this topic:
community.arm.com/.../embedded-world-2015---design-of-soc-for-high-reliability-systems-with-embedded-processors

Thanks,

Uma

Cortex-M7 has a parameter named LOCKSTEP to configure whether the implementation is a dual-redundant core.

It is related to functional safety requirements in certain types of microcontrollers/SoC for automotives and industrial applications. This allows logic failures to be detected, which enables safety features to kick in and start remedy actions.

The link below is a paper published in Embedded World 2015, which covered this topic:
community.arm.com/.../embedded-world-2015---design-of-soc-for-high-reliability-systems-with-embedded-processors

Thanks,

Uma