Architectures and Processors forum Setting MPU_RASR for Memory Protection Unit with correct values of TEX/C/B/S bits

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Setting MPU_RASR for Memory Protection Unit with correct values of TEX/C/B/S bits

d-r over 5 years ago

Hello,

I use LPC4078 with an Cortex-M4 core and would like to implement Memory Protection Unit (MPU). Therefore I need to set TEX/C/B/S bits in RASR register but unfortunately am not sure what would be the correct values. In Cortex-M4-User-Guide I only find this table:

I want to protect bootloader area in ROM memory space 0x0000 - 0x8000 (32k) from beeing erased or written. I would assume the following values:

ENABLE=1
SIZE=14 (32k)
SRD=0 (complete bootloader region active)
B=0 (not bufferable because it's ROM?)
C=1 (cacheable yes or no?)
S=1 (not shareable yes or no?)
TEX=0 (??? What would be normal here?)
AP=3 (Read only, by privileged or unprivileged software because I only want to prevent erasing and writing to bootloader area)
XN=0 (instruction fetches enabled?)

What about these values?

Regards,

Daniel