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Cortex M3 System Design - Simulation Environment

Brixton

Hi,
I followed the Arm Cortex-M System Design Kit - Example System Guide to establish simulation environment, but encountered some difficulties when I run "make compile" in terminal.

Warning-[STASKW_CO1] Cannot open file
  The file 'debugtester_le.hex' could not be opened. No such file or directory.
  Please ensure that the file exists with proper permissions.

Warning-[STASKW_RMCOF] Cannot open file
../../../logical/models/memories/cmsdk_ahb_ram_beh.v, 77
  Cannot open file 'debugtester_le.hex' passed as argument to $readmem.
  Please verify that the first argument to $readmem is a file that exists with proper permissions.

  • 0

    And? Is make right? Do these files exist or not?

  • 0 in reply to 42Bastian Schick

    not yet, error still exist..

    terminal:

    Starting vcs inline pass...
    68 modules and 0 UDP read.
        However, due to incremental compilation, no re-compilation is necessary.
    make[1]: make[1]: Entering directory `/ARM_IP/Corstone-101/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/systems/cortex_m_mcu/rtl_sim/csrc'
    Warning: File `rmapats.m' has modification time 0.016 s in the future
    make[1]: warning:  Clock skew detected.  Your build may be incomplete.
    make[1]: Leaving directory `/ARM_IP/Corstone-101/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/systems/cortex_m_mcu/rtl_sim/csrc'
    make[1]: Entering directory `/ARM_IP/Corstone-101/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/systems/cortex_m_mcu/rtl_sim/csrc'
    rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
    ld -shared  -Bsymbolic  -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o
    rm -f _csrc0.so
    if [ -x ../simv ]; then chmod -x ../simv; fi
    g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  -rdynamic  -Wl,-rpath=/tools/Synopsys/Vcs/O-2018.09-SP2/linux64/lib -L/tools/Synopsys/Vcs/O-2018.09-SP2/linux64/lib     _29091_archive_1.so _prev_archive_1.so _csrc0.so  SIM_l.o  _csrc0.so     rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o          -lnuma -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs /tools/Synopsys/Verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a    -lvcsnew -lsimprofile -luclinative /tools/Synopsys/Vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o   -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive        _vcs_pli_stub_.o   /tools/Synopsys/Vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o -ldl -lm  -lc -lpthread -ldl
    ../simv up to date
    make[1]: Leaving directory `/ARM_IP/Corstone-101/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/systems/cortex_m_mcu/rtl_sim/csrc'

    Warning-[STASKW_CO1] Cannot open file
      The file 'debugtester_le.hex' could not be opened. No such file or
      directory.
      Please ensure that the file exists with proper permissions.


    Warning-[STASKW_RMCOF] Cannot open file
    ../../../logical/models/memories/cmsdk_ahb_ram_beh.v, 77
      Cannot open file 'debugtester_le.hex' passed as argument to $readmem.
      Please verify that the first argument to $readmem is a file that exists with
      proper permissions.


    Warning-[STASKW_CO1] Cannot open file
      The file 'image.hex' could not be opened. No such file or directory.
      Please ensure that the file exists with proper permissions.


    Warning-[STASKW_RMCOF] Cannot open file
    ../../../logical/models/memories/cmsdk_ahb_ram_beh.v, 77
      Cannot open file 'image.hex' passed as argument to $readmem.
      Please verify that the first argument to $readmem is a file that exists with
      proper permissions.