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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Answered

    Cortex-R52+ asynchronous abort 0

    • abort
    • Cortex-R52+
    1167 views
    3 replies
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit 0

    • AMBA
    • AXI
    329 views
    0 replies
    Started 6 months ago
    by Manikanta Kopparapu
  • Not Answered

    Measured Boot Implementation with TF-A and OP-TEE on Jetson Orin Nano 0

    • secruity
    • measured boot
    • jetson orin nano
    • optee
    • jetpack
    953 views
    0 replies
    Started 6 months ago
    by Niklas Flink
  • Answered

    How to mapping MSI (LPIs) in Linux kernel 6.12.y ? +1

    1529 views
    3 replies
    Latest 6 months ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Multi-Master APB Subsystem 0

    370 views
    0 replies
    Started 6 months ago
    by Abdelrahman Ehsan
  • Suggested Answer

    Enable exceptions for dividing by zero float for CORTEX R7 0

    • Exception Handling
    • division by zero
    • Cortex-R
    • Floating-Point Execution
    • Cortex-R7
    880 views
    1 reply
    Latest 6 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Are Stage 1 & 2 walk repeat loops bounded? 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    2651 views
    5 replies
    Latest 6 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    Does integrated MCU consume memory bandwidth extremely, within a (Quad-A55 + MCU) SOC ? 0

    425 views
    0 replies
    Started 6 months ago
    by duanlin
  • Answered

    Amount of data that can be sent with one CMSIS-DAP data transfer command 0

    • DAP
    • CMSIS
    • CoreSight
    1873 views
    6 replies
    Latest 6 months ago
    by Oom Sats
  • Suggested Answer

    ARMv8 Cortex-A55 How to enable cache protection behavior 0

    • AArch64
    • Cortex-A55
    • Cache
    • Armv8-A
    871 views
    1 reply
    Latest 6 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    ARM CCA 0

    • cca
    932 views
    1 reply
    Latest 6 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    How is cache addressing assigned on the R5? 0

    • Cortex-R5
    1179 views
    3 replies
    Latest 6 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    A53 NEON memory access behavior 0

    • AXI4
    • Armv8-A
    • NEON
    • a53
    608 views
    1 reply
    Latest 6 months ago
    by Dylan Barrie
  • Answered

    Cortex-M33 wake up from SLEEPDEEP 0

    • nvic
    • Cortex-M33
    • Interrupt
    • WIC
    1264 views
    2 replies
    Latest 6 months ago
    by Yael Kanter-Weisman
  • Suggested Answer

    Ask a question about SME. 0

    972 views
    1 reply
    Latest 6 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    CHI TXLINK state deadlock possibility 0

    1594 views
    3 replies
    Latest 6 months ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Cleaning BSS in ARMv8-A 0

    • Clean
    • BSS
    • Cortex-A
    660 views
    1 reply
    Latest 7 months ago
    by Mahmud Esad Çıtak
  • Suggested Answer

    Is it possible to use the DBID as a conforming acknowledgement in CHI OWO process? 0

    • CHI
    • order
    1329 views
    2 replies
    Latest 7 months ago
    by Ming Gao
  • Suggested Answer

    AREADY/ARVALID and AWREADY/AWVALID for subsequent transfers in a burst 0

    949 views
    1 reply
    Latest 7 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    GIC-600 ITS MSI Handling: Who Writes the INT Command in the Command Queue? 0

    1520 views
    4 replies
    Latest 7 months ago
    by steve jeong
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