As the address for the subsequent transfers is calculated by slave, then there is no need of ARVALID/ARREADY and AWVALID/AWREADY for subsequent transfers.
1) So can these signals take any logic level or need to be logic high level for the rest of the burst ? Is ARADDR is updated with new address calculated by slave for subsequent transfer ?
2) Master can drive next valid write data only after WVALID and WREADY are asserted at same rising edge. Which means, only after the last write date is received by slave(indicated by assertion of WVALID and WREADY at same rising edge), master can drive valid write data. Pls confirm.