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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Not Answered

    TF-M PSA Crypto Random 0

    • PSA
    • TF-M
    1196 views
    4 replies
    Latest 5 months ago
    by Fran DP
  • Not Answered

    Unable to read currentel 0

    • a72
    • Armv8-A
    1059 views
    3 replies
    Latest 5 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    SOC sensor chips 0

    316 views
    0 replies
    Started 5 months ago
    by Brahm
  • Suggested Answer

    Difference between System mode, User mode and Supervisor mode in Cortex R. 0

    • Cortex R
    1023 views
    1 reply
    Latest 5 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    Cortex-R5F core unexpected fetch reserve address 0

    733 views
    1 reply
    Latest 5 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [ARM R52+] GIC distributor on R52+ with DCLS 0

    • GICv3/v4
    • Armv8-R
    839 views
    2 replies
    Latest 5 months ago
    by ShihHsun Chang
  • Not Answered

    Question about ITS Retry Behavior after Stalled MAPD Command 0

    765 views
    2 replies
    Latest 5 months ago
    by steve jeong
  • Suggested Answer

    AXI4 ordering Model. 0

    • AXI4
    856 views
    1 reply
    Latest 5 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Understanding Transaction Types in ARM Systems: Real-World Applications 0

    • ACE
    851 views
    1 reply
    Latest 5 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Understanding the Purpose and Configuration of DAP_ROMID 0

    • Cortex-R5
    1816 views
    6 replies
    Latest 5 months ago
    by ele
  • Not Answered

    Is there any way to use 2-DSU IPs in a same NI-Bus ? 0

    • DSU-120
    • DSU
    316 views
    0 replies
    Started 5 months ago
    by Sangu Park
  • Answered

    Secure Mode Switching in R5 0

    • cortexr5
    763 views
    1 reply
    Latest 5 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Request for Configuration and Usage Guide of PERIPH_PORT in Corinth 0

    • Cortex-A55
    • Cortex-A
    319 views
    0 replies
    Started 6 months ago
    by yiduan su
  • Answered

    What will happen when cacheline is mismatch 0

    • Cache
    • Cache Management
    • Cortex-A
    • Cortex-M
    953 views
    2 replies
    Latest 6 months ago
    by junhao.wang
  • Answered

    Does Cortex-A53 support Separate Start Address? 0

    • Cortex-A53
    784 views
    1 reply
    Latest 6 months ago
    by Yuping Luo Arm Employee Badge
  • Not Answered

    Cache Coherency for memory using SMMU V3 0

    • Cache coherency
    • SMMUv3
    • Cortex-A55
    • Cache Management
    417 views
    0 replies
    Started 6 months ago
    by Adithya SM
  • Suggested Answer

    Halt-on-debug scenario, halt the system counter when halting. 0

    • Cortex-A9
    • CoreSight Debug and Trace
    • Armv8-A
    • Cortex-A
    1619 views
    5 replies
    Latest 6 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    JDK 8 instructions f2xm1 and fyl2x, 80-bit extended precision implementation on ARM 0

    1513 views
    5 replies
    Latest 6 months ago
    by Jake Zhao
  • Answered

    How to generate LPI with ITS? 0

    790 views
    1 reply
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Use MSI(LPIs) in Linux kernel 6.12.y 0

    632 views
    1 reply
    Latest 6 months ago
    by steve jeong
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