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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    R5: Does the exception vector table reside in TCM if at 0x0000 0000 0

    • Armv7 Exception Model
    • Cortex-R5
    3510 views
    3 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    What these system registers(such as S3_3_c15_c7_0) are used for in Cortex-A55? 0

    • Cortex-A55
    • Armv8-A
    2709 views
    2 replies
    Latest over 2 years ago
    by Emmy0
  • Not Answered

    Is the PLD instruction implemented on the Arm Cortex M4, and actually preloading the cache line? 0

    • performance
    • Instruction Sets
    • Armv7-M
    • Cache Management
    • Cache Architecture
    • Cortex-M4
    768 views
    0 replies
    Started over 2 years ago
    by Toarte Fretter
  • Not Answered

    armRAL.h library in arm cortex -A9 0

    • Cortex-A9
    1051 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Suggested Answer

    FP4 datatype support on Cortex-M FPU? 0

    1450 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Cortex M4 - Access Level 0

    • Cortex-M4
    3371 views
    3 replies
    Latest over 2 years ago
    by Sudhu145
  • Not Answered

    TLB Broadcast serialization 0

    • AArch64
    • System architectures
    1630 views
    2 replies
    Latest over 2 years ago
    by ashmog Arm Employee Badge
  • Suggested Answer

    Interrupt servicing order on later arrived high priority interrupt with same subgroup. 0

    • Armv8-M
    1112 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    data coherency when NIC and CCI both used to access DDR 0

    747 views
    0 replies
    Started over 2 years ago
    by qp.harson
  • Suggested Answer

    Bare metal - EL2 to EL1 - SP behaviour 0

    3767 views
    7 replies
    Latest over 2 years ago
    by Chaudhary Shehwar Hussain
  • Answered

    Possible Documentation error in KBA Article ID: KA001775? +1

    • Documentation
    • PrimeCell DMA Controller (PL081)
    1887 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Can BLAS lib been used on Cortex-A9 based SOC baremetal system? 0

    • Cortex-A9
    • SoC FPGA
    1507 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Suggested Answer

    ARM R5F Static Registers 0

    1351 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    What should be LR(link register) value for Cortex-M7 core? 0

    • Cortex-M7
    • Cortex-M
    3410 views
    2 replies
    Latest over 2 years ago
    by TS_Sanshin
  • Not Answered

    Can I enchance Rreadnosnoop to accept dirty line? 0

    • ACE
    858 views
    0 replies
    Started over 2 years ago
    by luffy.bright
  • Not Answered

    Cortex-A53 Data Cache line allocation without reading memory 0

    • Cortex-A53
    • Armv8-A
    • Cache Management
    2569 views
    2 replies
    Latest over 2 years ago
    by Tapir
  • Suggested Answer

    Cortex R5 ARM processor 0

    • Cortex-R5
    8600 views
    13 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    [ATSAM3X8E] ADC Read thought process 0

    • Arduino Due
    678 views
    0 replies
    Started over 2 years ago
    by CedricAve1
  • Not Answered

    Define last transaction in CHI protocol 0

    • CHI
    860 views
    0 replies
    Started over 2 years ago
    by thinhduynguyen
  • Not Answered

    How to "clear" the source of dtb from video devices. 0

    729 views
    0 replies
    Started over 2 years ago
    by ziomario
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