Dear ARM expert,
I found that Cortex-A55 have some undocumented system registers.
I can't find the definition for these registers in the ARM Cortex A55 Technical Reference Manual.
Could you help describe what these system registers are for in Cortex A55?
What behavior if I write these registers? Are there any potential risk when I write them?
Thanks for your attention!
Best Regards,
Yan
The instruction syntax for MRS is shown here: MRS Xt, (S<op0>_<op1>_<Cn>_<Cm>_<op2>)
https://developer.arm.com/documentation/ddi0602/2023-06/Base-Instructions/MRS--Move-System-Register-to-general-purpose-register-?lang=en
So taking the first example:
That looks to me to be in the IMPDEF space (so processor specific rather than architecturally defined). The Cortex-A55 TRM gives a listing of the IMPDEF registers:
AArch64 implementation defined register summary
Looking up those values (annoyingly, the columns in the table aren't in the same order as the instruction syntax) it says the register is ATCR_EL1:
https://developer.arm.com/documentation/100442/0200/Register-descriptions/AArch64-system-registers/ATCR-EL1--Auxiliary-Translation-Control-Register--EL1?lang=en
It is helpful to me!
Thank you!