in my system， there are an exclusive L2 Dcache and several L1 Dcache. For some non-shareable cacheable memory region, one master (L1 dacahe) read and writeevict (with UD) to L2 dcache. when this L1 dcache using ReadNoSnoop read this line from L2 dcache again, we have some solutions:
1) L2 dcache pass a clean line to L1 dcache, and then writeback( with UD) to main memory (such as DDR)
2) L2 dcache pass a dirty line to L1 dcache and invalidate line in L2 dcache itself. but , this is no compatiable with ACE protocal ( RNS Rresp cannot pass dirty)
PPA of solution 1 is not very good, we want to implement solution 2, but we cannot sure , whether it is a good solution or property solution ?