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Thank you for your understanding.
I checked LR(link register) value about Cortex-M7 core with NUCLEO-H723ZG(STM32H723ZGT6).
As a result, when service routine is returned, LR value is PC address +1 as below.
PC=0x08001182
LR=0x08001183
Is this behavior correct one?
I expexted that LR and PC value are the same in this case.
The least significant bit in the LR register specifies that the code at this address is a Thumb instruction and all Cortex-M instructions have Thumb encoding. So this behavior is expected. All instructions of Cortex-M cores must be located on even addresses.
Thank you for your answer.
Which document gives your answer(The least significant bit in the LR register specifies that the code at this address is a Thumb instruction)?