Please note: We are aware of an issue affecting replies on the Arm Community forums, which may not be loading as expected.

We apologize for any inconvenience and appreciate your patience while we investigate and work to resolve the issue.

Thank you for your understanding.

  • State Not Answered
  • Locked Locked
  • Replies 0 replies
  • Subscribers 347 subscribers
  • Views 895 views
  • Users 0 members are here
Options
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Is the PLD instruction implemented on the Arm Cortex M4, and actually preloading the cache line?

Toarte Fretter

Dear,

From reading all the available Arm documentation, we're unable to confirm if the PLD Thumb2 instruction is actually preloading the referenced cache line on our Cortex M4. From testing, it looks like not giving any performance gains too? All we know is that the ID_ISAR2 register indicates it to be supported, as being mandatory for an Armv7-M device.

Question:

Is the indication of the support for the PLD instruction inside ID_ISAR2 actually also requiring to implement the preloading, or can it still be treated as a NOP by the processor instantiation?

Thanks in advance.

Kind regards,

Ignace.