Dear,
From reading all the available Arm documentation, we're unable to confirm if the PLD Thumb2 instruction is actually preloading the referenced cache line on our Cortex M4. From testing, it looks like not giving any performance gains too? All we know is that the ID_ISAR2 register indicates it to be supported, as being mandatory for an Armv7-M device.
Question:
Is the indication of the support for the PLD instruction inside ID_ISAR2 actually also requiring to implement the preloading, or can it still be treated as a NOP by the processor instantiation?
Thanks in advance.
Kind regards,
Ignace.