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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Not Answered

    Cache Coherency for memory using SMMU V3 0

    • Cache coherency
    • SMMUv3
    • Cortex-A55
    • Cache Management
    431 views
    0 replies
    Started 6 months ago
    by Adithya SM
  • Suggested Answer

    Halt-on-debug scenario, halt the system counter when halting. 0

    • Cortex-A9
    • CoreSight Debug and Trace
    • Armv8-A
    • Cortex-A
    1703 views
    5 replies
    Latest 6 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    JDK 8 instructions f2xm1 and fyl2x, 80-bit extended precision implementation on ARM 0

    1582 views
    5 replies
    Latest 6 months ago
    by Jake Zhao
  • Answered

    How to generate LPI with ITS? 0

    823 views
    1 reply
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Use MSI(LPIs) in Linux kernel 6.12.y 0

    664 views
    1 reply
    Latest 6 months ago
    by steve jeong
  • Answered

    Cortex-R52+ asynchronous abort 0

    • abort
    • Cortex-R52+
    1230 views
    3 replies
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit 0

    • AMBA
    • AXI
    340 views
    0 replies
    Started 6 months ago
    by Manikanta Kopparapu
  • Not Answered

    Measured Boot Implementation with TF-A and OP-TEE on Jetson Orin Nano 0

    • secruity
    • measured boot
    • jetson orin nano
    • optee
    • jetpack
    1073 views
    0 replies
    Started 6 months ago
    by Niklas Flink
  • Answered

    How to mapping MSI (LPIs) in Linux kernel 6.12.y ? +1

    1667 views
    3 replies
    Latest 6 months ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Multi-Master APB Subsystem 0

    379 views
    0 replies
    Started 6 months ago
    by Abdelrahman Ehsan
  • Suggested Answer

    Enable exceptions for dividing by zero float for CORTEX R7 0

    • Exception Handling
    • division by zero
    • Cortex-R
    • Floating-Point Execution
    • Cortex-R7
    913 views
    1 reply
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Are Stage 1 & 2 walk repeat loops bounded? 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    2739 views
    5 replies
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    Does integrated MCU consume memory bandwidth extremely, within a (Quad-A55 + MCU) SOC ? 0

    438 views
    0 replies
    Started 7 months ago
    by duanlin
  • Answered

    Amount of data that can be sent with one CMSIS-DAP data transfer command 0

    • DAP
    • CMSIS
    • CoreSight
    1976 views
    6 replies
    Latest 7 months ago
    by Oom Sats
  • Suggested Answer

    ARMv8 Cortex-A55 How to enable cache protection behavior 0

    • AArch64
    • Cortex-A55
    • Cache
    • Armv8-A
    911 views
    1 reply
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    ARM CCA 0

    • cca
    969 views
    1 reply
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    How is cache addressing assigned on the R5? 0

    • Cortex-R5
    1241 views
    3 replies
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    A53 NEON memory access behavior 0

    • AXI4
    • Armv8-A
    • NEON
    • a53
    631 views
    1 reply
    Latest 7 months ago
    by Dylan Barrie
  • Answered

    Cortex-M33 wake up from SLEEPDEEP 0

    • nvic
    • Cortex-M33
    • Interrupt
    • WIC
    1330 views
    2 replies
    Latest 7 months ago
    by Yael Kanter-Weisman
  • Suggested Answer

    Ask a question about SME. 0

    1007 views
    1 reply
    Latest 7 months ago
    by Ronan Synnott Arm Employee Badge
<>
Topics being discussed in this forum
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