Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    How to know thumb code or arm code? +1

    12218 views
    6 replies
    Latest over 8 years ago
    by 박주병
  • Answered

    Why Cortex-R5 Bus-ECC documentation different from Cortex-R7 0

    5101 views
    3 replies
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    why do we need two priviledged modes? cant one do the thing in cortex m3 +2

    • processor modes
    • Cortex-M3
    14809 views
    6 replies
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    arm7tdmi APMC_CGMR PLL +1

    4289 views
    3 replies
    Latest over 8 years ago
    by G. Goodwin L. Pitos
  • Answered

    Flash/RAM memory interfaces on Cortex-M7 based MCU for fast code execution 0

    • Cortex-M7
    11962 views
    1 reply
    Latest over 8 years ago
    by Yasuhiko Koumoto
  • Answered

    how cortex m4 processor executing inst from a 'C' file +1

    5517 views
    4 replies
    Latest over 9 years ago
    by daith
  • Answered

    Is it possible at all to inspect DCACHE line bytes (and flags) on the Cortex-A9 core by reading/writing CP14 or (less likely CP15)? +1

    • Cortex-A9
    • Cortex-A
    2699 views
    1 reply
    Latest over 9 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    How to use GPIO interface IPs of ARM Cortex M0+ +1

    • Cortex-M0
    • GPIO
    • Cortex-M
    • C
    • Interface
    8229 views
    4 replies
    Latest over 9 years ago
    by Sabarish
  • Not Answered

    Printing floats:    printf("t = %f", t) 0

    3681 views
    2 replies
    Latest over 9 years ago
    by Mariano Jimenez-Brenes
  • Answered

    GICv2 initialization for Non-Secure World +1

    • Generic Interrupt Controller
    • Cortex-A
    • Cortex-A7
    5538 views
    1 reply
    Latest over 9 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    Linaro support for ARM processor porting +1

    4455 views
    2 replies
    Latest over 9 years ago
    by Peter Bauer
  • Answered

    ARMv8 mmu for EL0/1and EL3 +1

    6191 views
    1 reply
    Latest over 9 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Secure world memory access with MMU disabled 0

    • Memory Management Unit (MMU)
    • TrustZone
    4531 views
    2 replies
    Latest over 9 years ago
    by Zizhu
  • Not Answered

    ARM Trusted Firmware Cluster Power Down Duration 0

    3030 views
    1 reply
    Latest over 9 years ago
    by daith
  • Answered

    Can't understand the difference between armv7e-m and armv7e-m-pic? 0

    • Armv7
    • Cortex-M7
    • Armv7-M
    • Digital Signal Processor (DSP)
    14178 views
    3 replies
    Latest over 9 years ago
    by Bilal Wasim
  • Answered

    Getting ERROR "unknown mnemonics for UQSUB8 instruction" 0

    • AArch64
    • Armv8-A
    • 64-bit
    12759 views
    4 replies
    Latest over 9 years ago
    by Myy
  • Answered

    Warning: It blocks containing 32-bit Thumb instructions are deprecated in ARMv8 with GCC 4.9 +1

    • 32-bit
    • Armv8
    • GCC
    • Cortex-M53
    • Thumb
    • Cortex-M
    13474 views
    4 replies
    Latest over 9 years ago
    by Michael Williams Arm Employee Badge
  • Answered

    Use-cases of AXI3 unaligned transfers +1

    • 32-bit
    • AXI3
    6353 views
    2 replies
    Latest over 9 years ago
    by Diandian Zhang
  • Answered

    I am working on ahb bridge , I am trying to sample address when hready is high . +1

    • AHB-Lite
    • AMBA 2
    • AHB
    7286 views
    4 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    Hard Fault in cortex m4 +1

    • Armv7-M
    • Memory Management Unit (MMU)
    • Cortex-M
    • Cortex-M4
    21793 views
    7 replies
    Latest over 9 years ago
    by Joseph Yiu Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone