I am using L2CC for level 2 cache controller, I configured to two master port. One master port will interface with AXI slave interface. However, since L2CC master port are AXI3, while AXI slave device are AXI4. The slave device doesn't support write data interleave. My question is, how do I make sure the L2CC won't make any data write interleave request?
Hi, neither L220 nor PL310 seems to have such a feature as prohibitting the write interleaving. I think you should take the only one way to insert AXI-AXI bridge (or AXI interconnect) which inhibit the write interleaving. Best regards, Yasuhiko Koumoto.