Have you initialized the SVC mode, and is the NS-bit configured as secure before you call cps?
My best guess is that you've got the NS-bit set to 1 (i.e. non-secure) and you switch modes, which drops the core in to non-secure SVC mode, because the NS-bit takes effect as soon as you drop out of monitor mode. It is quite possible that the PC you are using doesn't exist in the non-secure world, so it faults, but the non-secure exception table is also not set up, so that faults. Infinite loop of faults = hung CPU.
[color=#222222][size=2]Intention is to get the NS SVC mode SP
When we are trying to change the mode from Secure_Supervisor to NON_Secure_Supervisor, we go to Secure_monitor by invoking "SMC #0".
As part of the Secure_monitor handler when we try to write SCR register by executing "mcr p15, 0, r1, c1, c1, 0"instruction, core gets hard reset. The same code is working perfectly fine in FAST model. Find the below Secure_monitor handler implementation
Please let us know if there are any extra settings/configuration required, to work this out in hardware.
Let us know if you need any more information regarding this issue.
Thanks
Nisar