Hi folks,
in Armv8 reference manual, in the description of the VTTBR_EL2 register, the BADDR fields seems to have alignment constraints:
Translation table base address, bits[47:x]. Bits [x-1:0] are RES 0. The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of VTCR_EL2.T0SZ, the stage of translation, and the translation granule size.
However I'm a bit confused here. There are several computations of such an `x`, with no clear reference of the current scenario for each computation.
In Armv7 reference manual, the computation for this `x` was always clear for TTBR0, TTBR1, HTTBR, ...
In v8, I don't see any clear reference to the correct computation.
Where can I find the correct value of x for a aarch64 EL2 software, depending of level lookup, granule size and T0SZ ?
Best,
V.
Bonus question: I realise that the information is also hard to find for others TTBR, where I can I find each computation ?
Hi,
In the ARMv8-A Architecture Reference Manual (ARM DDI 0487A.j) §K7.1.1 `Examples of performing the initial lookup' it has some examples that I think explain what you're looking for.
These examples include the case where stage 2 involve concatenation of translation tables for the lookup to start at level 1, just in case you're setting VTCR_EL2.SL0.
Hope that helps,
Ash.
Thank you sir,
it is not as explicit as in v7 ARM, but that's good enough