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Cortex-A8 - accessing banked registers from monitor mode

Jitesh Shah
Note: This was originally posted on 20th March 2012 at http://forums.arm.com

Hi Group,
I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

I know two ways I can do it:

1) Using the "mrs" instruction.
eg. mrs r0, sp_svc

However, my compiler (code sourcery) says:
Error: Banked registers are not available with this architecture. -- `mrs r0,sp_svc'

My architecture manual does say that banked registers are accessible via this method, so I suppose this is a compiler issue. Anyway.

2) Changing the mode to svc, reading sp and getting back to the monitor mode.

eg. cps MODE_SVC
mov r0, sp
cps MODE_MON

where MODE_SVC = 0x13 and MODE_MON = 0x16

But, as soon as I execute "cps MODE_SVC" in monitor mode, my CPU hangs. There is no more activity.

So my question is this: Is SVC mode not accessible from Monitor mode? If thats not the case, how can I access SVC version of the registers from Monitor mode?

Thanks,
Jitesh
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    peterharris: Hi Peter,

    When we are trying to change the mode from Secure_Supervisor to NON_Secure_Supervisor, we go to Secure_monitor by invoking "SMC #0".

    As part of the Secure_monitor handler when we try to write SCR register by executing "mcr  p15, 0, r1, c1, c1, 0"instruction,  core gets hard reset. The same code is working perfectly fine in FAST model. Find the below Secure_monitor handler implementation

    Inline image 1

    Please let us know if there are any extra settings/configuration required, to work this out in hardware.

    Let us know if you need any more information regarding this issue.

    Thanks

    Nisar

Reply
  • 0

    peterharris: Hi Peter,

    When we are trying to change the mode from Secure_Supervisor to NON_Secure_Supervisor, we go to Secure_monitor by invoking "SMC #0".

    As part of the Secure_monitor handler when we try to write SCR register by executing "mcr  p15, 0, r1, c1, c1, 0"instruction,  core gets hard reset. The same code is working perfectly fine in FAST model. Find the below Secure_monitor handler implementation

    Inline image 1

    Please let us know if there are any extra settings/configuration required, to work this out in hardware.

    Let us know if you need any more information regarding this issue.

    Thanks

    Nisar

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