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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3631 Questions
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  • Not Answered

    arm cortex a9 used in control edge plc 0

    821 views
    0 replies
    Started over 3 years ago
    by saneesh
  • Not Answered

    .rodata alignment 0

    • AArch64
    • GNU Assembler
    1311 views
    0 replies
    Started over 3 years ago
    by BobP
  • Suggested Answer

    In order execution 0

    1268 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Suggested Answer

    How to control the Non-Secure MPU exclusively inside the Secure world in the Cortex M33? 0

    • Memory Protection Unit (MPU)
    • TrustZone
    • Cortex-M33
    1940 views
    1 reply
    Latest over 3 years ago
    by Aurelien_Grange
  • Not Answered

    start second core from psci 0

    • AArch64
    • SMCCC
    • Cortex-A55
    • Armv8-A
    • psci
    • AArch32
    1419 views
    0 replies
    Started over 3 years ago
    by Nikita bogatov
  • Suggested Answer

    Arm MMU configuration works on (qemu) raspberry(a53) but not on virt(armv7, a53) board 0

    • Cortex-A53
    3830 views
    5 replies
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [armv8][cortex-a72] why must flush data cache when I tried to map a SRAM area? 0

    • Armv8-A
    2468 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    CCA in Armv9 - Making Peripherals Only Accessible from a Realm VM 0

    • virtualization
    • Peripheral Controllers
    • TrustZone
    2123 views
    2 replies
    Latest over 3 years ago
    by Jay M.
  • Suggested Answer

    SError interrupt due to LDAXRB instruction when disable cache on NXP ls1046a 0

    • Armv8-A
    2316 views
    2 replies
    Latest over 3 years ago
    by Tony Tu
  • Suggested Answer

    Does the Arm Cortex-52+ support multi-core / cache coherent / SMP configurations? 0

    • Cortex-R52
    • Cache coherency
    • Cortex-R52+
    3348 views
    3 replies
    Latest over 3 years ago
    by EllieC Arm Employee Badge
  • Not Answered

    Clear recvBuff 0

    948 views
    0 replies
    Started over 3 years ago
    by Rishikeshb1998
  • Not Answered

    Power consumption of CM7 - is there a comparison between manufacturing nodes? 0

    899 views
    0 replies
    Started over 3 years ago
    by Tani
  • Answered

    CCA in Armv9 - Could Realm Management Monitor Check Realm VM's Data? 0

    • virtualization
    • Trusted Execution Environment (TEE)
    2215 views
    3 replies
    Latest over 3 years ago
    by djordje kovacevic Arm Employee Badge
  • Not Answered

    What signals, if any, can I omit from M0 verilog design when programming into FPGA? 0

    • Cortex-M0
    • FPGA
    1236 views
    0 replies
    Started over 3 years ago
    by BNguyen22
  • Not Answered

    Do we have any development board that supports Armv8.4 0

    1150 views
    0 replies
    Started over 3 years ago
    by irakatz
  • Answered

    cortex m7 frame pointer in prologue 0

    6097 views
    10 replies
    Latest over 3 years ago
    by Silicium
  • Answered

    armv8 write-back cache 0

    2297 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    6x6 Complex Matrix Inversion on the ARM Cortex M4F processor 0

    • Cortex-M4
    1753 views
    1 reply
    Latest over 3 years ago
    by Oliver Beirne Arm Employee Badge
  • Suggested Answer

    What should be the value of the WLAST signal if the length of the write burst is always equal to 0 0

    1521 views
    1 reply
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    About PSTRB... 0

    • APB
    1828 views
    1 reply
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
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