Does the Arm Cortex-52+ support multi-core / cache coherent / SMP configurations?

The Arm Cortex-R Comparison Table downloaded from Arm ( implies it does, but I have heard information contrary to this elsewhere.

Looking to understand the differences between the Cortex-R52+ and R52 and this MP support (coherency) seems to be one of a few along with support for virtualization extensions, etc.

So, is the R52+ cache coherent or not?