Does the Arm Cortex-52+ support multi-core / cache coherent / SMP configurations?

The Arm Cortex-R Comparison Table downloaded from Arm (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwibler1ifX5AhWOXvEDHY-QAwkQFnoECBIQAQ&url=https%3A%2F%2Fwww.arm.com%2F-%2Fmedia%2FArm%2520Developer%2520Community%2FPDF%2FCortex-A%2520R%2520M%2520datasheets%2FArm%2520Cortex-R%2520Comparison%2520Table.pdf&usg=AOvVaw116KiFKxN8hBF9IU4S1Bgv) implies it does, but I have heard information contrary to this elsewhere.

Looking to understand the differences between the Cortex-R52+ and R52 and this MP support (coherency) seems to be one of a few along with support for virtualization extensions, etc.

So, is the R52+ cache coherent or not?