hi there, i'm using A53 without OS, and configure memory attribute as write-back.
when i write a dword num to memory addr, i found that external reader could not read it as expect. then i change memory to non-cache, it works ok.
so, when write-back cache, how could i trig ddr update when i write a dword num?
Assuming the external reader is not a coherent device, then you would need to do a cache clean to the Point of Coherency (PoC). Something like "DC CVAC, Xt" where "Xt" holds the address you want to clean.