Hi Experts
My code runs in EL3 on ls1046a RDB in bare mental environment. Here are the focus code after start up.
Step 1: Disable data cache, the the sctlr_el3 is changed from 0x00c5183d to 0x00c51839
Step 2: Update a global variable.
Step 3: do {} while (atomic_flag_test_and_set(&gIRQpRrintmutex));
0000000080005a68: adrp x0, 0x8002e000 <__global_locale+120>0000000080005a6c: add x0, x0, #0x1b80000000080005a70: mov w1, #0x1 // #10000000080005a74: ldaxrb w2, [x0]
SError interrupt happened in Step 3: when execute "ldaxrb w2, [x0]" as the resister value as below:
ESR_EL3: 0xbf000002
ELR_EL3: 0x0000000080005a74
If not disable cache as in the step 1, the code execute well.
Any suggestion to fix the SError interrupt?
Thanks for response.
With a regular load, the Error goes way.
The Cortex A72 MPCORE TRM as below confirm your direction.
Internal coherent global monitor
If synchronization primitives are used for memory pages that are Shareable Normal Write-Back and the cache is enabled, SCTLR.C is 1, the external monitor on AXI is not used. Instead, the global monitor function is handled in the L1 cache using the cache coherence information.
External global monitor
If synchronization primitives are used for memory pages that are Device, or Inner-Shareable Normal Non-cacheable, a global monitor must be provided in the interconnect.
The interconnect CCI-400 used in LS1046A claimed to support the External global monitor. Not find the clue in LS1046A reference manual about NOT support External global monitor.
There are some note close to the exclusive access, but which is about Locked accesses:
" The CCI-400 has per core lock-reservation monitor individually for secure and non-secure exclusive (ARLOCK/AWLOCK) transactions (that is, a total of eight monitors). These transactions are terminated at the CCI level, as the system beyond CCI do not support the “lock transactions”. ..”.