What signals, if any, can I omit from M0 verilog design when programming into FPGA?

Hi all, 

Context/Background: I am a university student working on a research project with the goal of porting a Cortex M0 into an FPGA. Apologies in advance for any ignorance.

The main objective is to port the M0 into the FPGA, load a basic ARM program into the memory, and send data/control signals into a logic analyzer for review. If successful, this project will be used to teach future EE/CE students how to analyze real-time logical signals. 

I've been given access to the M0 verilog code through their academic access program. 


The device I have available is a TerAsic DE10-Lite and Quartus is telling me the design needs 13 more IO pins than the DE10-Lite can provide. As stated above, the only signals I really care about are the data/control signals but I know that many of these other signals are probably necessary for proper function of the core. 

Are there any signal wires I can omit from the pin assignments and just logically-tie so that I may no longer conflict with device constraints? I know that all variables will be used somewhere else so I won't delete from design. 

For example, I don't think we will be using a WIC at all. Will I destroy functionality if I "get rid" of these wires? 

Thanks in advance for any help! Please let me know if you need any further clarification.