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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 739 Questions
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  • Answered

    GIC 500 :: Not able to find the definition for GICD_IROUTERn register +1

    • CoreLink System Controllers
    • Corelink
    • CoreLink GIC-500 Generic Interrupt Controller
    5448 views
    2 replies
    Latest over 9 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    what are these axi transaction types mean? fixed, incremental, wrapped, reversed? Are there any docs descriped them in detail? +1

    • AMBA
    • AXI
    • Interface
    5882 views
    2 replies
    Latest over 9 years ago
    by bander
  • Not Answered

    Licensing FVP models 0

    • Arm Development Studio
    • Arm Compiler 6
    • Arm Cortex-R
    • Fixed Virtual Platforms
    • compiler
    • Arm Compiler
    4319 views
    1 reply
    Latest over 9 years ago
    by Mervyn Arm Employee Badge
  • Not Answered

    STM(System Trace Macrocell) 0

    • AMBA
    • AXI
    • system trace macrocell
    • Bus Architecture
    8243 views
    5 replies
    Latest over 9 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Why does AHB or APB support only 16 slave devices? +1

    • APB
    • AMBA
    • AXI
    • AHB
    • Interface
    12610 views
    4 replies
    Latest over 9 years ago
    by Ravindran
  • Not Answered

    Why the address boundary for AHB burst should not cross 1KB 0

    • AMBA
    • AHB
    13949 views
    1 reply
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    why there is no split or retry responce in AXI ? +1

    • AMBA
    • AXI
    • AHB
    9566 views
    2 replies
    Latest over 9 years ago
    by Jay Zhao
  • Not Answered

    In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst? 0

    • AMBA
    • System Architecture
    • Bus Architecture
    • AHB
    7115 views
    3 replies
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AHB HREADY low not after address phase +1

    • AMBA
    • System Architecture
    • Bus Architecture
    • AHB
    5944 views
    1 reply
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response? 0

    • AMBA
    • System Architecture
    • Bus Architecture
    • AHB
    16051 views
    9 replies
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Configuration options for cxapbic for 32 masters and 2 slaves +1

    • AMBA
    7236 views
    3 replies
    Latest over 10 years ago
    by Sid
  • Answered

    Partial Word Access to Altera Avalon Memory-Mapped Slave 0

    • AMBA
    • Arm Development Studio
    • FPGA
    • AXI
    7570 views
    1 reply
    Latest over 10 years ago
    by Qiangsheng Xiang
  • Answered

    AHB 0

    • AMBA
    • AMBA 2
    • AHB
    8008 views
    2 replies
    Latest over 10 years ago
    by VT
  • Answered

    AHB slave 0

    • AMBA
    • AHB
    14495 views
    11 replies
    Latest over 10 years ago
    by VT
  • Answered

    AHB Slave HREADY +1

    • AMBA
    • AHB
    7657 views
    1 reply
    Latest over 10 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    How can I get IP-XACT descriptions of CMSDK components? 0

    • APB
    • AMBA
    • CMSDK
    6874 views
    2 replies
    Latest over 10 years ago
    by Steven Dennis
  • Not Answered

    error when compiling ClockDiv_XilinxS6.v on Nexys3 0

    • Compilers
    4095 views
    1 reply
    Latest over 11 years ago
    by Mustapha
  • Not Answered

    Request for vendors: improve SPI/SSP 0

    4279 views
    2 replies
    Latest over 11 years ago
    by Jens Bauer
  • Not Answered

    by which instruction the secondary core is triggered while starting the secondary cpu 0

    • AArch64
    • Armv8
    • Linux
    5930 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    What flow should I execute to make cache and MMU work properly when I turn into non secure world? 0

    • mmu
    • Correx-A7
    • Cortex-A
    • TrustZone
    4758 views
    2 replies
    Latest over 11 years ago
    by Jay Zhao
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