Why the address boundary for AHB burst should not cross 1KB

The master doesn't know the physical makeup of the memory system, so if it did issue a burst that crossed from one physical slave to the next physical slave up in the address map, the 2nd slave wouldn't see a burst start with a NONSEQ access, and it wouldn't see the correct number of transfers issued if HBURST was signalling a defined length burst.

So by stating an address boundary that master bursts must not cross, this ensures that a burst that could cross between physical slaves will instead end at this boudary and restart on the other side of the boundary, that way both slaves will see correctly ending and starting bursts.

1KB would have been chosen as a compromise between supporting long bursts (for that you want the address boundaries to be larger) and supporting small slaves (you would want the address boundary to be smaller so as to avoid wasting address space as the boundary chosen also defines the minimum slave address range allocated by a decoder).

If a physical slave is larger than 1KB, this does then mean that it will see bursts end and restart when not crossing between slaves, so it can have an impact on performance on burst aware slaves (slaves that can perform transfers more efficiently when accessed by long defined length bursts), but as the master doesn't know if a 256KB SRAM address space is built from 1x256KB slave or 256x1KB slaves, this is the only safe way to ensure slaves will always see correctly starting and ending bursts.

Note that in the AXI protocol they chose 4KB as the address boundary, so supporting longer bursts, but also then meaning that each slave must occupy a minimum of 4KB.

JD

The master doesn't know the physical makeup of the memory system, so if it did issue a burst that crossed from one physical slave to the next physical slave up in the address map, the 2nd slave wouldn't see a burst start with a NONSEQ access, and it wouldn't see the correct number of transfers issued if HBURST was signalling a defined length burst.

So by stating an address boundary that master bursts must not cross, this ensures that a burst that could cross between physical slaves will instead end at this boudary and restart on the other side of the boundary, that way both slaves will see correctly ending and starting bursts.

1KB would have been chosen as a compromise between supporting long bursts (for that you want the address boundaries to be larger) and supporting small slaves (you would want the address boundary to be smaller so as to avoid wasting address space as the boundary chosen also defines the minimum slave address range allocated by a decoder).

If a physical slave is larger than 1KB, this does then mean that it will see bursts end and restart when not crossing between slaves, so it can have an impact on performance on burst aware slaves (slaves that can perform transfers more efficiently when accessed by long defined length bursts), but as the master doesn't know if a 256KB SRAM address space is built from 1x256KB slave or 256x1KB slaves, this is the only safe way to ensure slaves will always see correctly starting and ending bursts.

Note that in the AXI protocol they chose 4KB as the address boundary, so supporting longer bursts, but also then meaning that each slave must occupy a minimum of 4KB.

JD