Arm Community

Answered
With regard to slide 38 that talks about calling from secure code to non-secure code, can we assume that the registers pushed {r4-r11} cannot be viewed by examining the stack? +1
- TrustZone
- Armv8-M
7017 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Will a BLXNS into a location which is marked as secure, end up in the non-secure state, or will there be an exception? +1
- TrustZone
- Armv8-M
7128 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Is it possible to set a memory region from non-secure to secure at runtime? +1
- TrustZone
- Armv8-M
7381 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Does a library exist for Python to use the secure features of ARMv8-M or can they only be accessed using ASM or C/C++? +1
- TrustZone
- Armv8-M
7084 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
At what point in time is the boot security map fixed into the chip? +1
- TrustZone
- Armv8-M
6705 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
What sort of visibility does a non-secure debugger have of the secure sections? +1
- TrustZone
- Armv8-M
6590 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Can secure accesses access both secure and nonsecure address map, whereas, nonsecure only access nonsecure part of the address map. +1
- Armv8-M
6308 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
How did you measure the Instruction cache efficiency? Just code execution from Flash? Reading data from Flash? Programming data to Flash? +1
7191 views

1 reply

Latest over 8 years ago
by Mike EFTIMAKIS
Answered
Can you explain why you propose having two cores in your CoreLink SSE-200? +1
8096 views

1 reply

Latest over 8 years ago
by Mike EFTIMAKIS
Answered
Is the Corelink SSE-200 Subsystem available for Cortex M23? +1
- Corelink
- Cortex-M23
- Cortex-M3
- Cortex-M
- CoreLink SSE-200
- Cortex-M33
- Armv8-M
6512 views

1 reply

Latest over 8 years ago
by Mike EFTIMAKIS
Answered
Working frequency on AMBA- APB,AHB, AXI +2
- APB
- AMBA
- AXI
- AHB
- Interface
18891 views

1 reply

Latest over 8 years ago
by Colin Campbell
Suggested Answer
Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ? +1
- APB
- AMBA
16675 views

4 replies

Latest over 8 years ago
by Colin Campbell
Answered
RMW operation on SRAM via AXI +1
- AMBA
- AXI
- SRAM
7412 views

1 reply

Latest over 8 years ago
by Colin Campbell
Answered
AXI narrow read with unaligned address 0
- AMBA
- AXI
10037 views

2 replies

Latest over 8 years ago
by jduarte
Not Answered
AXI 0
- AMBA
- AXI
- Interface
6464 views

3 replies

Latest over 8 years ago
by Simone Secchi
Answered
AXI read transfer +1
- AMBA
- ACE
- AXI
- Interface
9958 views

1 reply

Latest over 8 years ago
by Martin Weidmann
Not Answered
read transfers 0
- AMBA
- AXI
- Interface
4212 views

1 reply

Latest over 8 years ago
by Martin Weidmann
Answered
AXI +1
- AMBA
- AXI
- amba4
- Interface
5891 views

2 replies

Latest over 9 years ago
by Muthuvenkatesh
Answered
GIC500 :: How to forward interrupts to multiple cores using GICD_IROUTER +1
- CoreLink System Controllers
- CoreLink GIC-500 Generic Interrupt Controller
9073 views

4 replies

Latest over 9 years ago
by Martin Weidmann
Answered
GIC500 :: Not able to disable Affinity Routing +1
5375 views

2 replies

Latest over 9 years ago
by danish259

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With regard to slide 38 that talks about calling from secure code to non-secure code, can we assume that the registers pushed {r4-r11} cannot be viewed by examining the stack? +1

Will a BLXNS into a location which is marked as secure, end up in the non-secure state, or will there be an exception? +1

Is it possible to set a memory region from non-secure to secure at runtime? +1

Does a library exist for Python to use the secure features of ARMv8-M or can they only be accessed using ASM or C/C++? +1

At what point in time is the boot security map fixed into the chip? +1

What sort of visibility does a non-secure debugger have of the secure sections? +1

Can secure accesses access both secure and nonsecure address map, whereas, nonsecure only access nonsecure part of the address map. +1

How did you measure the Instruction cache efficiency? Just code execution from Flash? Reading data from Flash? Programming data to Flash? +1

Can you explain why you propose having two cores in your CoreLink SSE-200? +1

Is the Corelink SSE-200 Subsystem available for Cortex M23? +1

Working frequency on AMBA- APB,AHB, AXI +2

Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ? +1

RMW operation on SRAM via AXI +1

AXI narrow read with unaligned address 0

AXI 0

AXI read transfer +1

read transfers 0

AXI +1

GIC500 :: How to forward interrupts to multiple cores using GICD_IROUTER +1

GIC500 :: Not able to disable Affinity Routing +1