AXI

The signals used to transfer data (RDATA and WDATA) are split into lanes, where each lane is 8 bits. So a 32-bit bus would give you four lanes.

Lanes become important when you are transferring quantities of data smaller than the bus width. For example, a 16-bit write on a 32-bit bus.

For why it matters, see chapter 9 of the AMBA4 AXI specification.
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