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Partial Word Access to Altera Avalon Memory-Mapped Slave

Qiangsheng Xiang

when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

Background:

In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

I am responsible for the board and FPGA design. Another software engineer is developing software under DS5 environment.

Avalon MM Slave interface is use on FPGA side.

Problem description:

Everything works fine on Altera System Console. However, it behaves differently when the software engineer debug his code on DS5.

He has problem to read data out from an address that is not multiple of 4.

For example, he can read a word (32-bit), or a half-word (16-bit), or a byte from address 0x800, but he cannot read anything from address 0x802 (always returned zeros).

Troubleshooting being conducted:

I thought it relates to where the data should be put on the 32bit data bus.  So I revised FPGA code to duplicate the data on the 32-bit bus,

but DS5 still reads all zeros.

Also tried to run SignalTap to capture waveforms, but DS5 and SignalTap

cannot be run at the same time through the same JTAG connector.

anybody know what could be the problem?

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    I just resolved the problem yesterday.

    The problem is with the byteenable signal generated by the
    AXI-Avalon bridge. It is asserted to correct value for only one clock cycle.

    To access address 0x802, the byteenable needs to be “1100”, and
    it should maintain the same value during the entire transaction. However, it
    only stay effective for one clock cycle then changed to different value.

    I have to revise my FPGA code to latch the byteenable signal,
    and use the latched value in my FPGA logic.

     

    The Avalon Master used by Altera System Console generates the
    correct byteenable signal during the entire transaction. That is why my FPGA
    works well on System Console, but failed on DS-5. 

     

     

Reply
  • 0

    I just resolved the problem yesterday.

    The problem is with the byteenable signal generated by the
    AXI-Avalon bridge. It is asserted to correct value for only one clock cycle.

    To access address 0x802, the byteenable needs to be “1100”, and
    it should maintain the same value during the entire transaction. However, it
    only stay effective for one clock cycle then changed to different value.

    I have to revise my FPGA code to latch the byteenable signal,
    and use the latched value in my FPGA logic.

     

    The Avalon Master used by Altera System Console generates the
    correct byteenable signal during the entire transaction. That is why my FPGA
    works well on System Console, but failed on DS-5. 

     

     

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