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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 729 Questions
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  • Answered

    How correctly control the Non-Sequential Strobe of axi4? 0

    • AXI4
    1917 views
    3 replies
    Latest 9 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    why is final state of Readunique not fixed to UD? 0

    • CHI
    1570 views
    3 replies
    Latest 9 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Can NONSEQ in first cycle of HRESP change to IDLE? Can that happen if NONSEQ is targeting a different peripheral? 0

    964 views
    1 reply
    Latest 9 months ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    AHB/AHB-LITE/AHB_5 How to handle Last transfer error of a BURST Transaction ??? 0

    • AMBA
    • AHB-Lite
    • AMBA 5
    • AHB
    1355 views
    1 reply
    Latest 9 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI4 data-less write transactions 0

    • AXI5
    2168 views
    4 replies
    Latest 10 months ago
    by ib-gardiner
  • Not Answered

    Does Tarmac generate in Post-Simulation? 0

    • tarmac
    1404 views
    2 replies
    Latest 10 months ago
    by ele
  • Suggested Answer

    Aligned address and wrap boundary calculation in AXI4 0

    2431 views
    1 reply
    Latest 10 months ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Beginner in ARM Socrates 0

    • socrates
    660 views
    0 replies
    Started 11 months ago
    by Sarath Kumar
  • Suggested Answer

    NIC-400 Interconnect implementation-defined ID bits on the Zynq UltraScale+? +1

    • CoreLink NIC-400
    1793 views
    1 reply
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Capturing PSTATE 0

    • AMBA
    1210 views
    1 reply
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    how to reset axi master can cause axi bus deadlock in soc design 0

    1387 views
    1 reply
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Reboot failing in FVP RDV2 platform +1

    • rdv2
    • tf-a
    • fvp
    • Neoverse Reference Design
    1386 views
    2 replies
    Latest 11 months ago
    by Toshihisa Oishi Arm Employee Badge
  • Suggested Answer

    In AXI-5, can BVALID be asserted on same cycle as WLAST? 0

    • AMBA 4
    • AXI5
    • AXI4
    • AMBA 5
    1277 views
    1 reply
    Latest 11 months ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    How is the "Bank" in A53's L2MERRSR defined in TRM? 0

    • apu
    • a53
    630 views
    0 replies
    Started over 1 year ago
    by User_0182
  • Answered

    CHI.F document typo issue in Table B4.3 0

    • AMBA
    • AMBA 5 CHI
    1759 views
    3 replies
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    ARM Fast Models and ELF sections physical size info 0

    570 views
    0 replies
    Started over 1 year ago
    by FredericH
  • Answered

    AXI write strobes forcing read-modify-write access? 0

    • AXI
    • AXI4
    1979 views
    2 replies
    Latest over 1 year ago
    by Etienne Valentin
  • Not Answered

    connecting CMN600AE to mali GPU 0

    679 views
    0 replies
    Started over 1 year ago
    by andyostler
  • Answered

    I have some question about address map in the Bus Matrix of AMBA5. 0

    2924 views
    5 replies
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    SIE-200 exclusive monitor about hexokay_m signal 0

    • Corelink
    • Bus Architecture
    • AMBA5
    724 views
    0 replies
    Started over 1 year ago
    by yangfang
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